HBM4 vs HBM3E: what doubles, and why it matters
HBM4 doubles the I/O count to 2,048, delivering over 2TB/s per stack against HBM3E's 1.2TB/s
The three lines
- HBM4 doubles I/O pins from 1,024 to 2,048 and channels from 16 to 32, taking per-stack bandwidth past 2TB/s
- The base die moves from a memory process to a foundry logic process, improving power efficiency by more than 40%
- Unit cost rises, but accelerator throughput gains more, because memory bandwidth binds before compute does
Key questions
- What is the difference between HBM4 and HBM3E
- HBM4 doubles the interface width from 1,024 to 2,048 I/O and the independent channels from 16 to 32, so per-stack bandwidth roughly doubles. Its base die also shifts from a memory process to a foundry logic process.
- How fast is HBM4
- The JEDEC standard specifies 8Gbps per pin, or about 2TB/s per stack. SK hynix has demonstrated operation above 10Gbps, exceeding the standard, and the spec allows up to 16-high stacks at 64GB.
- Why does HBM4 matter for AI chips
- Accelerator performance hits a memory-bandwidth ceiling before it hits a compute ceiling. Doubling per-stack bandwidth lifts both training and inference throughput and improves energy per token.
Every major memory supplier has now moved HBM4 out of the lab. SK hynix said on its Q2 2026 earnings call that it began shipping HBM4 in the second quarter and had closed long-term supply agreements with roughly ten customers; Samsung shipped commercial HBM4 in February; Micron has said its 12-high ramp is running at twice the pace of HBM3E. The generation that succeeds HBM3E as the default memory for AI accelerators is here. What follows is what actually changed, drawn from the JEDEC standard and supplier statements rather than roadmap slides.
1. What changed
The headline change is the width of the road, not the speed limit. Under JESD270-4, HBM4 doubles the I/O count from 1,024 to 2,048 and independent channels from 16 to 32. Per-stack bandwidth therefore roughly doubles without pushing per-pin speed to a difficult place — a deliberate choice, because signal integrity and power both degrade quickly as pin rates climb.
The second change is less visible and matters more for the industry's structure. The base die that sits underneath the stack and manages data flow moves from a memory process to a foundry logic process. That allows far more capable control circuitry, and it makes memory vendors dependent on foundry partners for a component they previously made themselves. The boundary between memory manufacturing and logic manufacturing is now blurred in a way it was not two generations ago.
2. The numbers
JEDEC sets the standard pin rate at 8Gbps, which yields roughly 2TB/s per stack. SK hynix has stated it achieved operation above 10Gbps; a straight conversion puts that near 2.5TB/s, though no supplier publishes a throughput figure at that speed. Against HBM3E 12-high — 36GB at roughly 1.2TB/s — the per-stack gap is close to a doubling, and suppliers cite power efficiency gains above 40% versus the prior generation.
| HBM3E | HBM4 | |
|---|---|---|
| I/O pins | 1,024 | 2,048 |
| Independent channels | 16 | 32 |
| Pin speed | up to 9.6Gbps | 8Gbps standard; above 10Gbps demonstrated |
| Bandwidth per stack | about 1.2TB/s | over 2TB/s |
| Stack height and capacity | 12-high, 36GB in production | up to 16-high, 64GB in spec |
| Base die | memory process | foundry logic process |
| Power | — | over 40% better efficiency (supplier figure) |
That gap is the whole argument for the generation. An accelerator's usable throughput is bounded by how fast it can be fed, not by how fast it can multiply — a large language model reads its entire parameter set from memory for each token it produces. Doubling bandwidth per stack moves the ceiling directly. Higher stacks and a logic base die do raise unit cost, and market researchers broadly expect HBM4 to price above HBM3E, but no supplier has published a number.
3. What is still open
Several things commonly reported as settled are not. The 12nm-class foundry process said to be used for SK hynix's base die has not been confirmed by the manufacturer. Pricing is entirely unpublished. The timing for 16-high 64GB parts — allowed by the spec but not yet in volume — remains unannounced, as does the schedule for HBM4E, for which samples have shipped against a 2027 production target.
Heat is the constraint least discussed and most likely to bind. Stacking higher and clocking faster raises total dissipation even as efficiency per bit improves, and cooling design increasingly decides which parts a customer can actually deploy. SK hynix has said it is developing an approach it calls iHBM that lowers thermal resistance by more than 30%; nothing comparable has been detailed publicly by its competitors.